Forming multi-layered interconnections with fluorine compound treatment permitting selective deposition of insulator
US5420075A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Apr 14, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/98
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.