Method for maintaining bus integrity during testing
US5420871A · kind A · utility
3Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1994 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Mar 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3183
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The integrity of a bus (16) may be maintained in a circuit (10) during testing by first scrutinizing the circuit to learn whether a potential conflict will ever exist on the bus for any combination of input values to the circuit. If no conflict will ever exist, then the bus is deemed a no-conflict bus, and nothing further need be done to that bus during testing. Should the bus be found to be a potential conflict bus, then a bus justification vector is generated for application to the circuit to maintain the integrity of the bus intact during testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.