Method of manufacturing a fully planarized MOSFET and resulting structure
US5422289A · kind A · utility
44Cited by
27References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 27, 1992 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Apr 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for forming MOSFET devices on a semiconductor substrate including steps of depositing layers of polysilicon, dielectric, and polysilicon again. Each polysilicon layer is planarized after it is deposited. The dielectric layer is patterned and etched to delineate active regions and interconnect grooves. After the second polysilicon layer is planarized, the material in the active region is patterned and etched to form a gate and source and drain areas. The appropriate areas of the active region are doped as necessary to form the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.