Integrated circuit chip placement in a high density interconnect structure
US5422513A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1993 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Oct 4, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.