Automatic cache flush with readable and writable cache tag memory
US5423019A · kind A · utility
50Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1993 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Oct 26, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chipset is provided which permits reading and writing to cache tag memory for testing purposes and for writing non-cacheable tags into tag RAM entries to effectively invalidate the corresponding cache data entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.