Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode
US5424657A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1994 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The level shifter provides a selective voltage level shift to a common mode signal level on a twisted pair signal line. The level shift is selectively performed based upon the input level of the common mode voltage. The level shifter is advantageously employed in a low voltage circuit wherein lacking sufficient voltage head room to accommodate a constant common mode level shift. An exemplary embodiment is described wherein the level shifter is employed within a bus transceiver of a bus system employing IEEE P1394 bus protocol. In the exemplary embodiment, the selective level shift is applied only to bus signals occurring during an idle phase and an arbitration phase, with no level shift performed during a data phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.