DECL logic gates which operate with a 3.3 volt supply or less
US5424660A · kind A · utility
1Cited by
11References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1993 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Jun 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.