Self-timing random access memory
US5424980A · kind A · utility
10Cited by
31References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1994 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Feb 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory (RAM) includes a plurality of sensing circuits. During a read operation, the RAM detects that one of the sensing circuits has sensed a binary digit. In response, the read operation is terminated and an idle operation is initiated to provide a self-timing RAM. During a write operation, the data which is stored in a RAM cell is also sensed by one of the sensing circuits and the memory detects that one of the sensing circuits has sensed the stored data. In response, the write operation is terminated and an idle operation is initiated. Self-timing read and write operations are thereby provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.