Memory cell with programmable antifuse technology
US5426614A · kind A · utility
44Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 13, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jan 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell (10) comprising a first antifuse (A1) operable to place the memory cell (10) in a non-volatile state. In one embodiment, the memory cell (10) comprises a pair of cross-coupled inverters (I1,I2). The first antifuse (A1)is connected between an output (B) of one of the cross-coupled inverters and ground and is operable to place the memory cell in a first non-volatile state. A second antifuse (A2) is connected between an output (B) and a supply voltage (Vcc) and is operable to place the memory cell (10) in a second non-volatile state. Only one of the antifuses, (A1 or A2) is programmed in memory cell (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.