Full scan optimization technique using drive one/drive zero elements and multiple capture clocking
US5426650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jul 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques may be used with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a .phi.1 clock signal or .phi.2 clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.