Method of making a MOS device with drain side channel implant
US5427963A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0221
Abstract
An MOS device is provided having a drain- or source-side implant into the channel region in order to minimize short-channel effects. Implant into the channel region is achieved using conventional processing techniques, wherein the channel implant is directed substantially perpendicular to the upper surface of the substrate. Numerous masking steps and reorientation of the substrate is not needed. Additionally, the drain- or source-side implant mask can be formed from currently existing masks and incorporated into a standard processing flow for either a standard MOS device or a memory array comprising dual-level polysilicon. If drain-side implant is chosen, then the lateral demarcation line between the drain implant and the substrate is preferably placed within the channel region, and preferably near a mid-point within the channel a spaced distance below a subsequently placed, overlying polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.