Down-bonded lead-on-chip type semiconductor device
US5428247A · kind A · utility
42Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor device wherein the down bonding and the mounting of multi-pin is made possible. A conductive member adhered to the bottom surface of the semiconductor element. The conductive member and the specific pad of the semiconductor element are connected by the connecting member, which enables the entire bottom surface of the semiconductor element to be used for down bonding. Further, the more effective latch-up suppression, noise dispersion and speed improvement compared with the conventional LOC-type package structure is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.