Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming
US5428304A · kind A · utility
6Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1994 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Jul 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.