Testing architecture with independent scan paths
US5428622A · kind A · utility
46Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1993 |
| Grant date | Jun 27, 1995 |
| Priority date | — |
| Expiry date | Mar 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first and second clocks are alternately enabled by a control signal initiated under program control of the external test system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.