Electrostatic discharge protection circuit

US5430595A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Glen R. Wagner · Beaverton, US
• Jeffrey E. Smith · Alpharetta, US
• Jose Maiz · Portland, US
• Clair Webb · Beaverton, US
• William M. Holt · Hillsboro, US

Key dates

• Filing date: Oct 15, 1993
• Grant date: Jul 4, 1995
• Expiry date: Oct 15, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

A device for protecting an integrated circuit (IC) against electrostatic discharge (ESD) includes a self-triggered silicon controlled rectifier (STSCR) coupled across the internal supply potentials of the integrated circuit. The STSCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR. The ESD protection device also includes diode clamps between the periphery and internal power supply lines, and a novel well resistor which provides a distributed resistance further protecting sensitive output buffer circuitry.