Clair Webb
11Patents
5h-index
18Co-inventors
63Inventor score
Filing activity: Jun 4, 1991 → Mar 24, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5228134A | Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus | Physics | 96 | Expired |
| US5293603A | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path | Physics | 72 | Expired |
| US5430595A | Electrostatic discharge protection circuit | Electricity | 62 | Expired |
| US9461143B2 | Gate contact structure over active gate and method to fabricate same | Electricity | 50 | Active |
| US8786040B2 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Electricity | 10 | Active |
| US10192783B2 | Gate contact structure over active gate and method to fabricate same | Electricity | 3 | Active |
| US9496486B2 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Electricity | 3 | Active |
| US6762464B2 | N-p butting connections on SOI substrates | Electricity | 0 | Expired |
| US11004739B2 | Gate contact structure over active gate and method to fabricate same | Electricity | 0 | Active |
| US9105839B2 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Electricity | 0 | Active |
| US12278144B2 | Gate contact structure over active gate and method to fabricate same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.