Ternary storage dynamic RAM
US5432735A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1993 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Jul 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus using conventional DRAMs which uses a ternary representation of stored data. Each DRAM memory cell can thus store three states. The ternary storage memory apparatus includes a binary to ternary converter which receives a first number of binary bits of data during a write operation and generates a second lesser number of data values or voltages using a ternary representation. A second number of memory storage elements are coupled to the binary to ternary converter and store the respective voltage using the above ternary representation. During reads, a ternary to binary converter reads the voltages stored in the memory elements and converts these voltages into the original first number of binary bits that were originally written into the memory storage elements. This allows the use of existing DRAM while considerably increasing the DRAM's memory storage density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.