Method and circuitry for minimizing clock-data skew in a bus system
US5432823A · kind A · utility
389Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1994 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Jan 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.