Non-destructive read ferroelectric based memory circuit
US5434811A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1989 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | May 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory circuit comprises cross-coupled transistors which drive first and second nodes to differential voltage states. First and second ferroelectric capacitors are connected respectively between the first and second nodes and a common node. The ferroelectric capacitors are set to opposite polarization states as a function of the voltage states at the first and second differential nodes. When power is lost from the circuit, the last data state in the circuit is stored in the ferroelectric capacitors. When power is restored to the memory circuit, the ferroelectric capacitors unbalance the differential nodes to such an extent to cause the circuit to become reestablished to the last data state stored in the circuit. An input signal can be received at one of the nodes through an input transistor to set the state of the memory circuit and the state of the circuit can be read from one of the nodes through an output transistor. The input and output transistors can be the same device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.