Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
US5434990A · kind A · utility
10Cited by
14References
4Claims
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Key dates
| Filing date | Aug 6, 1990 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Aug 6, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reading data from an n-way, set associative cache. n individually addressable memory units are provided, with each of the units storing a plurality of data elements. All n of the units are concurrently addressed to transfer a data element from each of the units to a respective latch, and one of such data elements is selectively transferred from one of the latches. The units are then serially addressed in a predetermined pattern to sequentially transfer data elements out of the units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.