Synchronous/asynchronous clock net with autosense
US5434996A · kind A · utility
73Cited by
4References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1993 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Dec 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is operating in a synchronous or asynchronous fashion, while the circuit still minimizes clock skew between the internal bus clocks of both clock domains as well as any corresponding external bus clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.