Electrically programmable integrated memory with only one transistor
US5436479A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1992 |
| Grant date | Jul 25, 1995 |
| Priority date | — |
| Expiry date | Nov 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel electrically programmable and erasable memory cell, comprising a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain and the floating gate. The capacitive coupling between the source and the floating gate is low, as is normally the case. Preferably, the control gate only partly covers the floating gate. Another part of the floating gate is covered by a semiconductor layer connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.