Method of fabricating field effect transistor having polycrystalline silicon gate junction
US5438007A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1993 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Sep 28, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.