Semiconductor memory using low power supply voltage
US5438543A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1994 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Apr 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral/refresh control circuit for a semiconductor memory device, e.g., a dynamic random access memory (DRAM), which includes a first pull-up device connected between a supply voltage and the pull-up node of a sense amplifier, the first pull-up device having a first mode of operation wherein the power supply voltage is coupled to the pull-up node and a second mode of operation wherein the power supply voltage is isolated from the pull-up node, a second pull-up device coupled between a boosting voltage and the pull-up node, the second pull-up device having a first mode of operation wherein the boosting voltage is coupled to the pull-up node and a second mode of operation wherein the boosting voltage is isolated from the pull-up node, a first pull-up control circuit for selectively switching the first pull-up device between its first and second modes of operation, and a second pull-up control circuit for selectively switching the second pull-up device between its first and second modes of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.