Inventor · San Diego, CA, US

Sei Seung Yoon

105Patents
17h-index
80Co-inventors
89Inventor score

Filing activity: Nov 25, 1992 → Oct 18, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US8144509B2 Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size Emerging Cross-Sectional Technologies 56 Active
US8107280B2 Word line voltage control in STT-MRAM Physics 43 Active
US6958931B1 Bit line control and sense amplification for TCCT-based memory cells Physics 37 Expired
US8482966B2 Magnetic element utilizing protective sidewall passivation Electricity 36 Active
US5315557A Semiconductor memory device having self-refresh and back-bias circuitry Physics 36 Expired
US8971096B2 Wide range multiport bitcell Physics 35 Active
US5781494A Voltage pumping circuit for semiconductor memory device Physics 30 Expired
US6735113B2 Circuit and method for implementing a write operation with TCCT-based memory cells Physics 27 Expired
US8027206B2 Bit line voltage control in spin transfer torque magnetoresistive random access memory Physics 27 Active
US7742329B2 Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory Physics 26 Active
US7324394B1 Single data line sensing scheme for TCCT-based memory cells Physics 24 Active
US5796293A Voltage boosting circuits having backup voltage boosting capability Physics 22 Expired
US7345937B2 Open digit line array architecture for a memory array Physics 22 Active
US6079023A Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals Physics 22 Expired
US7764537B2 Spin transfer torque magnetoresistive random access memory and design methods Physics 21 Active
US6903987B2 Single data line sensing scheme for TCCT-based memory cells Physics 19 Expired
US7995378B2 MRAM device with shared source line Physics 17 Active
US6529423B1 Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device Physics 16 Expired
US9202555B2 Write word-line assist circuitry for a byte-writeable memory Physics 16 Active
US7813166B2 Controlled value reference signal of resistance based memory circuit Physics 16 Active
US9646681B1 Memory cell with improved write margin Physics 15 Active
US6721220B2 Bit line control and sense amplification for TCCT-based memory cells Physics 15 Expired
US9030863B2 Read/write assist for memories Electricity 14 Active
US5953259A Integrated circuit memory devices having cross-coupled isolation gate controllers which provide simultaneous reading and writing capability to multiple memory arrays Physics 13 Expired
US5438543A Semiconductor memory using low power supply voltage Physics 13 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.