Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories
US5438546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1994 |
| Grant date | Aug 1, 1995 |
| Priority date | — |
| Expiry date | Jun 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory includes a first and a second output, a main array having a first and a second column, and a redundant array having a first and a second redundant column. A logic includes a first and a second CAM set. The first CAM set activates the first redundant column to replace the first column if defective. The second CAM set activates the second redundant column to replace the second column if it is defective. A configuration circuit is provided for controlling the logic to selectively couple the first and second columns and the first and second redundant columns to the first and second outputs. When the configuration circuit is in a first state, the logic couples the first redundant column to the first output if it is activated and the second redundant column to the second output if it is activated. When the configuration circuit is in a second state, the logic couples (1) the first redundant column to the first and second outputs when the first column is defective and addressed, (2) the second column to the first and second outputs when the second column is addressed and the first column is defective, or (3) the second redundant column to the first and second outputs …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.