Substrate for producing semiconductor wafer
US5439723A · kind A · utility
17Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1993 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Nov 12, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24777
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
A semiconductor wafer includes a notch or a hole used in preparing an orientation flat on the wafer. The notch in the wafer includes a side that is perpendicular to the surfaces of the wafer and aligned along a cleavage plane of the wafer for forming the orientation flat by cleaving. A hole in a wafer preferably includes an axis aligned along the cleaving plane. A sharp, non-rounded cleavage is formed by preparing the notch or hole after the completion of any etching processes or other steps that may round the edges of the flat. The sharp edges aid in achieving a precision alignment using the orientation flat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.