Method for fabricating a CMOS device with reduced number of photolithography steps
US5439834A · kind A · utility
13Cited by
7References
2Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 15, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Nov 15, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
Abstract
In a method for fabricating a CMOS device with NMOS and PMOS transistors, patterned nitride films are employed in the source/drain ion implantation procedure to reduce the required number of photolithography steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.