Self-aligned source/drain MOS process
US5439839A · kind A · utility
186Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Jul 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned contact process for making an MOS device results in an MOS device with a small and repeatable interconnect size, repeatable interconnect resistance, and reduced source/drain junction capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.