Write control for a memory using a delay locked loop
US5440514A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Mar 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.