Delay locked loop for detecting the phase difference of two signals having different frequencies
US5440515A · kind A · utility
88Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Mar 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.