Semiconductor integrated circuit device
US5440521A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 19, 1993 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Aug 19, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps betwee…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.