System and method for saving state information in a multi-execution unit processor when interruptable instructions are identified
US5440703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1993 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Sep 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method provides additional logic in both execution units of a dual execution unit processing in order to determine if the instruction is interruptable. Additionally, backout logic is provided for saving the contents of unique registers. The backout logic uses two decodes to determine if the instruction currently executing modifies the unique registers. It is possible for a single instruction to modify more than one unique register. The backout logic of the present invention resides in both of the execution units and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers, then the contents of that register are saved in a backout latch. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.