Emulation of segment bounds checking using paging with sub-page validity
US5440710A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1994 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Mar 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by extending the paging system to allow for valid regions that are less than the full page size. Sub-page validity can mimic segmentation because a segment can be broken up into a number of full pages and one or more partially-valid pages at the segment boundaries. A page that is not wholly valid has an "event" on the page, and a memory reference to this page will either cause a software routine to be invoked to check the segment bound, or an extension to the TLB, called a sub-page validity buffer, is used to check if the reference was to a valid portion of the page. Events may also be defined for program watchpoints and defective memory locations. Segment bounds thus do not have to be compared for each access, and the bounds do not even have to be stored on the CPU die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.