Exponential Technology, Inc.
34Patents
0Active
34Granted
36Portfolio score
Filing activity: Jan 11, 1994 → Apr 23, 1997
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5598546A | Dual-architecture super-scalar pipeline | Physics | 284 | Expired |
| US5477082A | Bi-planar multi-chip module | Electricity | 236 | Expired |
| US5732209A | Self-testing multi-processor die with internal compare points | Physics | 182 | Expired |
| US5481684A | Emulating operating system calls in an alternate instruction set using a modified code segment descriptor | Physics | 155 | Expired |
| US5781750A | Dual-instruction-set architecture CPU with hidden software emulation mode | Physics | 148 | Expired |
| US5745913A | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks | Physics | 131 | Expired |
| US5781457A | Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU | Physics | 125 | Expired |
| US5481693A | Shared register architecture for a dual-instruction-set CPU | Physics | 121 | Expired |
| US5542059A | Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order | Physics | 112 | Expired |
| US5551001A | Master-slave cache system for instruction and data cache memories | Physics | 93 | Expired |
| US5685009A | Shared floating-point registers and register port-pairing in a dual-architecture CPU | Physics | 84 | Expired |
| US5692152A | Master-slave cache system with de-coupled data and tag pipelines and loop-back | Physics | 76 | Expired |
| US5664159A | Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register | Physics | 72 | Expired |
| US5477489A | High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver | Physics | 71 | Expired |
| US5608886A | Block-based branch prediction using a target finder array storing target sub-addresses | Physics | 71 | Expired |
| US5440710A | Emulation of segment bounds checking using paging with sub-page validity | Physics | 69 | Expired |
| US5884057A | Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor | Physics | 67 | Expired |
| US5687336A | Stack push/pop tracking and pairing in a pipelined processor | Physics | 61 | Expired |
| US5634118A | Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation | Physics | 58 | Expired |
| US5644752A | Combined store queue for a master-slave cache system | Physics | 57 | Expired |
| US5757690A | Embedded ROM with RAM valid bits for fetching ROM-code updates from external memory | Physics | 55 | Expired |
| US5542109A | Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities | Physics | 52 | Expired |
| US5652872A | Translator having segment bounds encoding for storage in a TLB | Physics | 51 | Expired |
| US5784590A | Slave cache having sub-line valid bits updated by a master cache | Physics | 49 | Expired |
| US5453949A | BiCMOS Static RAM with active-low word line | Physics | 39 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.