Semiconductor heterostructure devices with strained semiconductor layers
US5442205A · kind A · utility
201Cited by
11References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 9, 1993 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Aug 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.