Sign-extension of immediate constants in an alu
US5442577A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1994 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Mar 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for every bit in a full-width operand. The operands or constants are input to the select inputs for the muxes while signals representing the truth table for a predetermined Boolean operation are inputted to the four data inputs of each of the muxes. This allows for many different kinds of Boolean operations to be executed by the Boolean logic unit; each type of Boolean operation called for by an instruction opcode will have a corresponding set of truth table signals for input to the muxes. Sign-extension can be combined with the Boolean operation by using the sign bit of the reduced-width operand to select one of two modified sets of truth-table signals. The selected set of truth-table signals is applied to the data inputs of the muxes. An upper section of the truth-table sets has the sign bit of the reduced width operand encoded into the truth-table sets themselves. The integer arithmetic unit uses ex…
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