Fast data compression circuit for semiconductor memory chips including an array built-in self-test structure
US5442641A · kind A · utility
37Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1994 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Apr 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast high-density data compression circuit adapted to semiconductor integrated circuits of the memory type including an ABIST unit. This circuit, which compares the data-out signals output by the memory unit with the expected data generated by the ABIST unit to deliver a signal on a cycle by cycle basis, which is indicative of the fail/no fail status of the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.