Method for manufacturing an integrated circuit having at least one MOS transistor

US5443992A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Lothar Risch · Neubiberg, DE
• Thomas Vogelsang · Mountain View, US
• Franz Hofmann · Munich, DE
• Karl Robert Hofmann · Netphen, DE

Key dates

• Filing date: Nov 1, 1994
• Grant date: Aug 22, 1995
• Expiry date: Nov 1, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a channel region and a drain region for the MOS transistor is produced in the first opening by epitaxial growth of semiconductor material within situ doping. A second opening that is at least of a depth corresponding to the sum of the thicknesses of drain region and channel region is produced in the layer structure, a gate dielectric is applied on the surface thereof and a gate-electrode is applied on said gate dielectric.