Apparatus for fast internal reference cell trimming
US5444656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Jun 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having memory devices arranged in rows and columns, each column including a load device across which a first voltage level is provided when a memory device being read is in one condition and a second voltage level is provided when a memory device being read is in a second condition, a reference device arranged in series with another load device, a sensing device for detecting the voltages across the load devices and providing a first output signal when the voltage across the first load device is greater than the voltage across the second voltage device and a second output when the voltage across the first load device is less than the voltage across the second voltage device. The array also includes an arrangement for decoupling the memory devices and the associated load devices and applying a precise voltage equivalent to the one of the voltages across the load device while programming the reference devices so that the voltage across the second load device is compared to this precise voltage when the reference device is being programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.