Memory module with address error detection
US5444722A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1993 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Feb 17, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a match signal when the read address is within a selectable address range for the storage cells. Also, the module further includes: a control circuit, coupled to the compare circuit, which responds to the match signal by almost always executing the read command in a small time interval on the bus and occasionally executing the read command in a long time interval. Further, the module includes a bus transmit circuit, coupled to the control circuit, for sending a control signal on the bus if the control circuit selects the long time interval. Also, the module includes an error circuit, coupled to the control circuit and the bus, for setting an error flag if the control circuit selects the short time interval and, during that short time interval, the control signal is detected on the bus from another module in the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.