Dan T. Tran
11Patents
7h-index
12Co-inventors
63Inventor score
Filing activity: Jan 11, 1993 → Jul 22, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5511224A | Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories | Physics | 67 | Expired |
| US5598421A | Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits | Physics | 48 | Expired |
| US5809533A | Dual bus system with multiple processors having data coherency maintenance | Physics | 22 | Expired |
| US5293621A | Varying wait interval retry apparatus and method for preventing bus lockout | Physics | 21 | Expired |
| US5666515A | Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address | Physics | 20 | Expired |
| US5553249A | Dual bus adaptable data path interface system | Physics | 14 | Expired |
| US5495573A | Error logging system with clock rate translation | Physics | 10 | Expired |
| US5293496A | Inhibit write apparatus and method for preventing bus lockout | Physics | 7 | Expired |
| US5444722A | Memory module with address error detection | Physics | 5 | Expired |
| US10488062B2 | Geofence plus schedule for a building controller | Mechanical Engineering; Lighting; Heating | 3 | Active |
| US10302322B2 | Triage of initial schedule setup for an HVAC controller | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.