Cross-cache-line compounding algorithm for scism processors
US5446850A · kind A · utility
25Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1994 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Jul 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time the numerically preceding instruction in cache is transferred to the instruction compounding unit and instructions from the two lines are compounded. If a numerically preceding cache line has been compounded with a cache line that has been deleted and then replaced, compounding tags for the numerically preceding cache line are deleted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.