Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles
US5448704A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Mar 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PCI bus writes non-contiguous data in a maximum of two PCI bus write cycles. A Bridge is provided which can combine data within its write buffer such that non-contiguous data results. Some I/O devices on the PCI bus cannot handle non-contiguous data, so the Bridge detects non-contiguous data, and generates appropriate write cycles to the PCI bus to transfer this data in a contiguous fashion. The method described takes advantage of the multiple data phase capability of the PCI bus to transfer data at more than one address during one PCI bus write cycle, and optimizes these transfers to assure that all non-contiguous transfers can occur in only two PCI bus write cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.