RISC microprocessor architecture implementing fast trap and exception state
US5448705A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1993 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | May 24, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section of a prefetch buffer and executing said fetched instructions. The method also provides for handling interruptions to the processing of the main instruction stream and allowing return to the main instruction stream without requiring prefetching of instructions already fetched. Similarly, the method provides for handling interruptions of the processing of interruptions of the processing of the main instruction stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.