Johannes Wang
70Patents
26h-index
19Co-inventors
81Inventor score
Filing activity: Jan 8, 1992 → May 6, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5560032A | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Physics | 165 | Expired |
| US5438668A | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer | Physics | 135 | Expired |
| US5497499A | Superscalar risc instruction scheduling | Physics | 95 | Expired |
| US5557763A | System for handling load and/or store operations in a superscalar microprocessor | Physics | 94 | Expired |
| US5539911A | High-performance, superscalar-based computer system with out-of-order instruction execution | Physics | 91 | Expired |
| US5619666A | System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Physics | 88 | Expired |
| US5961629A | High performance, superscalar-based computer system with out-of-order instruction execution | Physics | 85 | Expired |
| US5689720A | High-performance superscalar-based computer system with out-of-order instruction execution | Physics | 69 | Expired |
| US5546552A | Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Physics | 62 | Expired |
| US5826055A | System and method for retiring instructions in a superscalar microprocessor | Physics | 59 | Expired |
| US5448705A | RISC microprocessor architecture implementing fast trap and exception state | Physics | 58 | Expired |
| US5659782A | System and method for handling load and/or store operations in a superscalar microprocessor | Physics | 56 | Expired |
| US6775761B2 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor | Physics | 48 | Expired |
| US5394515A | Page printer controller including a single chip superscalar microprocessor with graphics functional units | Physics | 47 | Expired |
| US5481685A | RISC microprocessor architecture implementing fast trap and exception state | Physics | 45 | Expired |
| US5737624A | Superscalar risc instruction scheduling | Physics | 43 | Expired |
| US6230254A | System and method for handling load and/or store operators in a superscalar microprocessor | Physics | 39 | Expired |
| US6282630A | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Physics | 35 | Expired |
| US6965987B2 | System and method for handling load and/or store operations in a superscalar microprocessor | Physics | 35 | Expired |
| US5564117A | Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units | Physics | 34 | Expired |
| US6131157A | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor | Physics | 33 | Expired |
| US6128723A | High-performance, superscalar-based computer system with out-of-order instruction execution | Physics | 32 | Expired |
| US5832292A | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Physics | 32 | Expired |
| US7000097B2 | System and method for handling load and/or store operations in a superscalar microprocessor | Physics | 31 | Expired |
| US6647485B2 | High-performance, superscalar-based computer system with out-of-order instruction execution | Physics | 28 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.