Address generator for multi-channel circular-buffer style processing
US5448706A · kind A · utility
35Cited by
12References
25Claims
0Family size
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Key dates
| Filing date | May 13, 1992 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | May 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one-chip address generator for producing a sequence of address signals for application to a memory containing a plurality of circular buffers. The address generator chip is capable of processing service requests from a plurality of channels on a prioritized basis. Service requests can arrive asynchronously at different rates. A channel-specific length or overlap value can be assigned to each servicing of a request. A seamless pipeline structure is provided for processing the service requests of subsequent channels immediately after completion of service for a first requesting channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.