ESD/EOS protection circuits for integrated circuits
US5450267A · kind A · utility
26Cited by
2References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1993 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.