Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions
US5450605A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1993 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Jan 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.