Method for manufacturing a memory cell
US5451535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | May 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
Abstract
A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.